Automotive radar solutions for advanced driver assistance systems (ADAS) are currently being deployed on a large scale. These solutions can typically be grouped into long range radar (LRR) applications and short range radar (SRR) applications. Both of these applications generally use frequency modulated continuous wave (FMCW) modulation techniques in order to be able to identify a radar target, such as a car or a pedestrian.
These radar systems typically utilise millimeter wave (MMW) frequencies for transmission and reception. In current Automotive Radar systems, several receivers and transmitters are often implemented in a single radar device in order to improve the system sensitivity, range and resolution, in order to achieve a better target identification. In such systems, especially in the receiver section, variable gain amplifier stages (VGA) and saturation detectors (SD) are often used in order to detect the presence of strong interferers that may saturate receiver components or circuits, and then compromise the received signal integrity. By combining the saturation detection function with the automatic gain control (AGC) of the variable gain stages, it is possible to maintain the received signal inside a suitable range, thereby allowing the microcontroller unit (MCU) to correctly proceed with the signal processing and interpretation thereof.
In a multistage/multichannel radar receiver context, all saturation detection signals are typically combined into a single output, largely to save cost in providing multiple saturation detectors outputs and reduce pin or ball count and as shown in FIG. 1. Typically, the combining function is implemented using an ‘OR’ logic gate, whereby a trigger is raised if any of the saturation detection signals identifies a saturation event.
FIG. 1 schematically shows a known integrated circuit 100 comprising gain components and saturation detectors employed in a radar device. The illustrated integrated circuit 100 is a three receiver/channel radar device. For simplicity, only one of the stages/channels will be described in detail. Referring to the first receiver/channel 150, a received radio frequency (RF) signal 102 is down-converted by mixer 104 when mixed with a local oscillator signal to produce an intermediate frequency or baseband signal 106. The intermediate frequency or baseband signal 106 output from mixer 104 is subsequently passed to a first gain stage 112. Concurrently, the intermediate frequency or baseband signal 106 output from mixer 104 is also input to a first saturation detector 114, to determine whether the signal has been subject to saturation in the mixer 104. The first gain stage 112 comprises a high pass filter 108 and a variable gain amplifier (VGA) 110. If the first saturation detector 114 detects a saturation event, the first saturation detector 114 outputs a logic ‘1’ to an input of a second saturation detector 116. Otherwise, if the first saturation detector 114 does not detect a saturation event, it outputs a logic ‘0’ to the input of the second saturation detector 116.
An output of the first gain stage 112 is coupled to an input of a second gain stage 120. Concurrently, the output of the first gain stage 112 is also coupled to a further input of the second saturation detector 116. The second saturation detector 116 comprises a logic ‘OR’ gate 122, which receives the output from the first saturation detector 114 and an output from the second saturation detector 116. In this manner, the second saturation detector 116 outputs a logic ‘1’ in response to receiving a saturated output from the first gain stage 112 or an indication of a saturation event in the mixer 104 from the first saturation detector 114. If either, or both, of the outputs received by the logic ‘OR’ gate 122 signify a saturation event, the logic ‘OR’ gate outputs a logic ‘1’ to an input of a third saturation detector 124. Otherwise, the logic ‘OR’ gate outputs logic ‘0’ to the input of the third saturation detector 124. The second gain stage 120 comprises similar components to the first gain stage 112 and is arranged to provide its output to a third saturation detector 124. The operation of the third saturation detector is the same as the second saturation detector 116. The output 128 of the third saturation detector 124 is input to a buffer 130, comprising a three input logic ‘OR gate 132 for receiving the saturation detector output from each of the receiver/channels and an output drive stage 134. If, for example, the output 128 from the first receiver/channel comprises an indication of a saturation event, in a form of a logic ‘1’, which is signaled via output 136 to an external controller (not shown). The external controller then reduces the gain of all of the gain stages across all of the receivers/channels throughout the integrated circuit 100, in order to remove the saturation event.
However, besides providing an advantage in respect of a higher integration level and reduced pin/ball counting, this solution does not allow a possibility to discover which channel or receiver, or which gain stage within the radar receiver is saturating. In such a case, the AGC that reduces a gain of a given amplifier stage gain if a saturation is detected applies the gain reduction in all receive channels and stages at the same time. As such, the identification of a saturation event and the treatment of this results in a robust, non-accurate and non-specific reduction in signal level across all channels, thereby resulting in loss of receiver sensitivity, inefficiency and sub-optimal signal level range.
In modern radar devices and systems, pins/balls counting and power consumption must both be drastically reduced in order to decrease the IC package size and cost, and also to facilitate customer integration with a simpler board. In such a context, outputting each individual saturation detector output on a dedicated pin is also not a viable solution.